The fields of technology include integrated circuit structures and processes for making them.
Processes of making integrated circuit structures have line widths of microscopic dimensions currently measured in nanometers (nm). Process generations having different size line widths from each other, and thought of in general, are called process nodes. An integrated circuit or “chip” generally has a semiconductor substrate (e.g. silicon, silicon germanium or gallium arsenide or other substance), or instead may have an insulating layer, on which semiconductor devices like transistors and diodes are fabricated. Over the semiconductor devices, alternating layers of insulator and conductor are provided, like a layer cake on a cake pan. The conductor layers are patterned and etched into microscopic conducting lines (sometimes called wires and that may have rectangular cross-sections) that are analogous to, but extremely small compared with, say, ordinary electrical conducting wires having a round cross-section as used for home wiring.
The conducting lines are used to interconnect the semiconductor devices to make integrated circuits of varying complexity that under a microscope look like a grid of streets, except at many levels. The conductor layers often are metal but any electrical conductive substance can be useful. The metal layers are called Metal-1 (MET1), Metal-2 (MET2), etc. in order counting upward from above the substrate. Conductive studs called vias are made or deposited through one or more of the insulating layers to electrically connect the conductor layers. Sometimes, the term “via structure” is also used to refer to the combination of conductors and/or their geometry connected with one or more vias. Conductive studs are called contacts when they connect the conducting lines at a lower level to integrated semiconductor devices.
To actually implement a particular desired electronic circuit that has been designed and defined by a netlist of the functional electronic circuits, a form of computer software and system, called a layout tool or place-and-route tool or simply a tool, is used to situate and define the geometric arrangement of the conducting lines, vias and their interconnections with the semiconductor devices. Tools have constraints, called design rules, that are consistent with the process capabilities and also provide some simplification or order for mathematical algorithms or procedures adopted in a tool to lay out a given complicated integrated circuit and avoid what would otherwise a stupefying and unnecessarily complicated array of geometric possibilities in three dimensions of height, width and depth for the conducting lines that the tool is to define. Structures, placements or geometries that do not conform with design rules are forbidden, and called “illegal” in the technological sense used in this art.
In a process node, such as 45 nm (45 nanometers) and smaller, it is believed that in at least some tools, the vias are or will be constrained by a design rule to be on a fixed grid pattern, or gridded via structure. This problematically causes significant inefficiency in the implementation of redundant vias (multiple vias per connection) and introduces an unfortunate impact due to what are called porosity problems. A convenient degree of porosity is important because the conducting lines for a process should be able, or need be able, to intertwined among each other like spaghetti going in various in-out, side-to-side, and up-down directions so that a comprehensive and flexible arrangement of the conducting lines is possible to interconnect the semiconductor devices in almost any desired way to realize any particular desired functional electronic circuits. If no impact to gridded routing with a single via arises, redundant and multiple-via structures are still impacted by porosity problems.
As the semiconductor industry progresses over time, the via resistance is increasing rapidly from node to node increasing the need for redundant vias, not only for good process yield and convenient porosity, but also low wire resistance and via resistance control from a performance perspective. Increasing via resistance and wire resistance in successive process nodes can limit signal propagation delays (picoseconds/millimeter) below the clock speed that is possible to use with high performance transistors in an integrated circuit fabricated at that process node. Such a problem is called wire-limiting, and may be addressed with wide wires (permissions for wider width conducting lines).
However, wide wires present a porosity problem, as illustrated in FIG. 1, because the width of the wide wires obscures or blocks some portions of the chip where vias might otherwise be provided. Routing porosity is vital and critical for optimizing integrated circuit and silicon cost in terms of number of metal levels and in terms of design efficiency (number of drcs or design rule checks). In FIG. 1, for example, two wide wires 110 and 112 on successive metal levels are connected by a via 120. The wide wires 110 and 112 do not just cover places 122, 124, 126 where vias could potentially be situated, like narrower wires would. The wide wires 110 and 112 further and additionally block or prevent placement of other wide wires over places 131, 132, 133, 134, 135, 136, 137, 138 where other wide wires and vias might potentially have been situated, and thus porosity is reduced.
For illustration, to simplify the drawings as shown in FIG. 1, grid locations that are unused for vias are denoted by “x” and each grid location actually used for a via (called a “placed via”) is represented by a darkened square and an “x”. Conductors at different conductor levels or layers are represented contrastingly, or simply with intersecting or overlapping outlines.
In FIGS. 2-3, another conventional approach arrays some vias on either a 2×1 array, or a 2×2 or larger array of vias covered with a rectangle of metal overlying all the vias in the array. However, the FIG. 2 case of 2×1 presents a large resistance due to the narrow metal, thereby trading off conductivity for compact routing. In a first case in FIG. 2, a segment 140 of conductor at one conductor level is connected with an inverted-L segment 142 at a next-lower level or next-higher level by two vias 151 and 152. In a second case nearby in FIG. 2, a segment 160 of conductor at one conductor level is connected with an inverted-L segment 162 at a next such level by two vias 171 and 172. Via 171 connects a connecting stub or segment 164 for segment 160 with the inverted-L segment 162. Either way, the result presents large resistance, especially as the industry progresses to advanced process nodes.
Moreover, in the case of 2×2 array depicted in FIG. 3, the very large piece of covering metal forces wide metal spacing and an increased routing hazard that lacks porosity as it blocks one or more other conductive lines from occupying a 3×3 array. If wide wire is used, a fifth, central via in FIG. 3 is added in a case called 2×2+1, but the tradeoff of porosity for lower resistance remains. In FIG. 3, wide wires 180 and 182 at successive metal levels are connected by vias 191-194 at corners of the 3×3 array. A further, fifth via 195 may be provided centrally in this low-porosity metal-covered array.
In FIG. 4, this problematic situation is further intensified under a design rule for gridded via layout that imposes a minimum spacing dimension d on potential via x's in both row (“horizontal”) and column (“vertical”) dimensions or permutations at each metal level. Moreover, the design rule not only has minimum spacing (all permutations) for gridded vias but also no horizontal or vertical adjacency allowed. FIG. 4 shows the no-adjacency rule in operation near a region 210 of placed vias having a neighboring placed-via 212. At some distance from via 212, a pair of vias 214 is displaced away horizontally from a site 215 of potential placement. Site 215 is termed a “skip grid” here because it is skipped to situate the via pair 214 under the design rule. In FIG. 4, the X 215 is chosen to be skipped in that the via 214 could optionally be placed in either location 215 or 214. A placed via prohibits another via from being placed in either horizontally and vertically adjacent locations, but not the diagonally adjacent locations. Locations 214 and 215 are not obstructed by any other via. This deviates from a strict regular grid where the via would have to be placed at 215. The skip grid allows the via to be shifted horizontally and/or vertically by a single grid location as long as it does not violate the above adjacency rule.
In FIGS. 5A and 5B, the no-adjacency design rule also forbids instances 1×2 array 230, 2×2 array 220, a 3×3 square array (not shown), and other orthogonal arrays. The rule can apply even with infinite isolation from other grids, meaning numerous unused via locations “x” surrounding each such array. The large X over each of FIGS. 5A and 5B represents the forbidden nature of each of these two layouts.
Accordingly, significant departures and alternatives in structures, circuits, and processes for addressing the above considerations and problems would be most desirable.